Embedded Target for Motorola MPC555

QADC Analog In

Input driver enables use of Queued Analog-Digital Converter (QADC64) in continuous scan mode

Library

Embedded Target for Motorola MPC555

Description

The QADC Analog In block sets the QADC64 into continuous scan mode. It then samples the specified channels at the specified rate. In continuous scan mode, the analog-to-digital converter is scanned as fast as possible, at a rate much faster than the sample rate of the model. Using continuous scan mode ensures that your application will obtain the latest signal value.

The MPC555 has two QADC modules, A and B. You can program these individually. You can place only one instance of the QADC Analog In block per module in your model or subsystem.

Dialog Box

QADC module

Selects module A or B.

Channels

A vector of numbers representing channels to be scanned. See Channel Number Selection below.

Justification

Converted data is read from the 10-bit wide QADC64 result word table into a 16-bit word. Data from the result word table can be accessed in three different formats. The Justification menu selects from the following formats:

• Right-justified (unsigned): with zeros in the higher order unused bits.
• Left-justified (signed): with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits. In this mode, zero is treated as the half scale of the input range.
• Left-justified (unsigned): with zeros in the unused lower order bits.
  Refer to section 13.13, in the "Queued Analog-to-Digital Converter Module-64" section of the MPC555 Users Manual for further information.

Sample time

Block sample time; determines sample rate at which the port is monitored.

Enable pass through (show simulation input)

Lets you provide a signal to this block for use in simulation. When this option is enabled, an inport appears on the block. The input (pass-through) signal must have double or single data type. The input signal is scaled onto the range 0..1 to represent the minimum and maximum voltage input. This input signal is mapped onto output according to the selected Justification option for justification. The Enable pass through option affects simulation only.

See also Data Type Support and Scaling for Device Driver Blocks.

Channel Number Selection

A channel number in the Channels vector selects the input channel number corresponding to the analog input pin to be sampled and converted. The analog input pin channel number assignments and the pin definitions vary, depending on whether the QADC64 is operating in multiplexed or nonmultiplexed mode. The queue scan mechanism makes no distinction between an internally or externally multiplexed analog input.

If a reserved channel number (channels 32 to 47) or an invalid channel number (channels 4 to 31 in nonmultiplexed mode), the low reference level (V_RL) is converted.

Programming the channel field to channel 63 indicates the end of the queue.

Channels 60 to 62 are special internal channels. When one of these channels is selected, the sample amplifier is not used. Instead, the value of V_RL, V_RH, or (V_RH - V_RL)/2 is placed directly into the converter. Programming the input sample time to any value other than two for one of the internal channels has no benefit except to lengthen the overall conversion time.

Table 5-1 and Table 5-2 show the mapping between the channel numbers and the hardware pins for the two scanning modes (multiplexed and nonmultiplexed).

For example, in nonmultiplexed mode, to scan all 16 channels of the QADC64 you would specify the following vector in the Channels field:

• [ 0 1 2 3 48 49 50 51 52 53 54 55 56 57 58 59 ]
  

Table 5-1: Nonmultiplexed Scan Mode  

Port Pin Name	Analog Pin Name	Other Functions	Pin Type (I/O)	Channel Number
PQB0 PQB1 PQB2 PQB3	A_AD0 / AN0 A_AD1 / AN1 A_AD2 / AN2 A_AD3 /AN3	- - - -	I I I I	0 1 2 3
- - PQB4 PQB5	- - A_AD4 / AN48 A_AD5 / AN49	Invalid Reserved - -	- - I I	4 to 31 32 to 47 48 49
PQB6 PQB7 PQA0 PQA1	A_AD6 / AN50 A_AD7 / AN51 A_AD8 / AN52 A_AD9 / AN53	- - - -	I I I I/O I/O	50 51 52 53
PQA2 PQA3 PQA4 PQA5	A_AD10 / AN54 A_AD11 / AN55 A_AD12 / AN56 A_AD13 / AN57	- - - -	I/O I/O I/O I/O	54 55 56 57
PQA6 PQA7 - -	A_AD14 / AN58 A_AD15 / AN59 V RL V RH	- - - -	I/O I/O I I	58 59 60 61
- -	- -	(VRH - VRL)/2 End of Queue Code	- -	62 63

Table 5-2: Multiplexed Scan Mode  

Port Pin Name	Analog Pin Name	Other Functions	Pin Type (I/O)	Channel Number
PQB0 PQB1 PQB2 PQB3	A_AD0 / ANw A_AD1 / ANx A_AD2 / ANy A_AD3 / Anz	- - - -	I I I I	0-14 even 1-15 odd 16-30 even 17-31 odd
- PQB4 PQB5 PQB6	- A_AD4 / AN48 A_AD5 / AN49 A_AD6 / AN50	Reserved - - -	- I I I	32-47 48 49 50
PQB7 PQA0 PQA1 PQA2	A_AD7 / AN51 - - -	- MA0 MA1 MA2	I I I/O I/O I/O	51 52 53 54
PQA3 PQA4 PQA5 PQA6	A_AD11 / AN55 A_AD12 / AN56 A_AD13 / AN57 A_AD14 / AN58	- - - -	I/O I/O I/O I/O	55 56 57 58
PQA7 - - -	A_AD15 / AN59 V RL V RH -	- - - (VRH - VRL)/2	I/O I I -	59 60 61 62
-	-	End of Queue Code	-	63

In Table 5-2, PQA0, PQA1 and PQA2 are used as output pins to drive an external demultiplexer.

MPC555 Resource Configuration

QADC Digital In