Embedded Target for Texas Instruments C6000 DSPs    
Matrix Multiply

Perform matrix multiplication on two input signals

Library

C62x DSP Library--Math and Matrices

Description

The Matrix Multiply block multiplies two input matrices A and B. Inputs and outputs are real, 16-bit, signed fixed-point data types. This block wraps overflows when they occur.

The product of the two 16-bit inputs results in a 32-bit accumulator value. The Matrix Multiply block, however, only outputs 16 bits. You can choose to output the highest or second-highest 16 bits of the accumulator value.

Alternatively, you can choose to output 16 bits according to how many fractional bits you want in the output. The number of fractional bits in the accumulator value is the sum of the fractional bits of the two inputs.


 Input A
 Input B
 Accumulator Value
Total Bits
 16
 16
 32
Fractional Bits
 R
 S
 R + S

Therefore R+S is the location of the binary point in the accumulator value. You can select 16 bits in relation to this fixed position of the accumulator binary point to give the desired number of fractional bits in the output (see Examples below). You can either require the output to have the same number of fractional bits as one of the two inputs, or you can specify the number of output fractional bits in the Number of fractional bits in output parameter.

The Matrix Multiply block supports both continuous and discrete sample times. This block also supports both little-endian and big-endian code generation.

Dialog Box

Set fractional bits in output to
Only 16 bits of the 32 accumulator bits are output from the block. Choose which 16 bits to output from the list:
Number of fractional bits in output
Specify the number of bits to the right of the binary point in the output. This parameter is enabled only when you select User-defined for Set fractional bits in output to.

Algorithm

In simulation, the Matrix Multiply block is equivalent to the TMS320C62x DSP Library assembly code function DSP_mat_mul. During code generation, this block calls the DSP_mat_mul routine to produce optimized code.

Examples

Example 1 Suppose A and B are both Q.15. The data type of the resulting accumulator value is therefore the 32-bit data type Q1.30 (R + S = 30). In the accumulator, bits 31:30 are the sign and integer bits, and bits 29:0 are the fractional bits. The following table shows the resulting data type and accumulator bits used for the output signal for different settings of the Set fractional bits in output to parameter.

Set fractional bits in output to
 Data Type
 Accumulator Bits
Match input A
 Q.15
 b30:b15
Match input B
 Q.15
 b30:b15
Match high bits of acc.
 Q1.14
 b31:b16
Match high bits of prod.
 Q.15
 b30:b15

Example 2 Suppose A is Q12.3 and B is Q10.5. The data type of the resulting accumulator value is therefore Q23.8 (R + S = 8). In the accumulator, bits 31:8 are the sign and integer bits, and bits 7:0 are the fractional bits. The following table shows the resulting data type and accumulator bits used for the output signal for different settings of the Set fractional bits in output to parameter.

Set fractional bits in output to
 Data Type
 Accumulator Bits
Match input A
 Q12.3
 b20:b5
Match input B
 Q10.5
 b18:b3
Match high bits of acc.
 Q23.-8
 b31:b16
Match high bits of prod.
 Q22.-7
 b30:b15

See Also

Vector Multiply


  LMS Adaptive FIR Matrix Transpose