SimPowerSystems    

Description of the Control System

The control systems of the rectifier and of the inverter use the same 12-pulse HVDC Control block from the Controls library of powerlib_extras. The block can operate either in rectifier or inverter mode. Use the Look under mask to see how this block is built.

Inputs and Outputs

Input 1 (Vabc) is a vectorized signal of the three line-to-ground voltages measured at the primary of the converter transformer. These three voltages are used to synchronize the pulse generation on the line voltages. Inputs 2 and 3 are the DC line voltage (VdL) and current (Id). Note that the measured DC currents (IdR and IdI in A) and DC voltages (VdLR and VdLI in V) are scaled to p.u. (1 p.u. current = 2 kA; 1 p.u. voltage = 500 kV) before they are used in the controllers.

Inputs 4 and 5 (Vd_ref and Id_ref) are the Vd and Id reference values in p.u. The VdL and Id inputs are filtered before being processed by the regulators. A first-order filter is used on the Id input and a second-order filter is used on the VdL input. The filter parameters are shown in the dialog box of Figure 2-30.

Input 6 (Block) accepts a logical signal (0 or 1) used to block the converter when Block = 1. Input 7 is also a logical signal that can be used for protection purposes. If this signal is high (1), the firing angle is forced at the value defined in the block dialog box.

The first two block outputs (PulseY and PulseD) contain the vectorized signals of the six pulses to be sent to each of the six-pulse converters connected to the wye and delta windings of the converter transformer. The third output (alpha) is the firing delay angle in degrees ordered by the regulator. The fourth output (Id_ref_lim) is the actual reference current value (value of Id_ref limited by the VDCOL function as explained below).

Synchronization System

The Discrete 12-Pulse HVDC Control block uses the primary voltages (input 1) to synchronize and generate the pulses according to Vd_ref and Id_ref set points (inputs 4 and 5). The synchronizing voltages are measured at the primary side of the converter transformer because the waveforms are less distorted. The firing command pulse generator is synchronized to the fundamental frequency of the AC source. At the zero crossings of the commutating voltages (AB, BC, CA), a ramp is reset. A firing pulse is generated whenever the ramp value becomes equal to the desired delay angle provided by the regulator. In order to improve the commutating voltages used by the pulse generator, the primary voltages (Vabc) are filtered by a low Q second-order band-pass filter centered at the fundamental system frequency. The base system frequency and the filter bandwidth are defined in the block dialog box.

Steady-State V-I Characteristic

The Discrete 12-Pulse HVDC Control block implements this steady-state characteristic:

Figure 2-29: Rectifier and Inverter Steady-State Characteristics and VDCOL Function

In normal operation, the rectifier controls the current at the Id_ref reference value, whereas the inverter controls the voltage at the Vd_ref reference value. The Id_margin and Vd_margin parameters are defined in the inverter dialog box. They are set respectively at 0.1 p.u. and 0.05 p.u. The system normally operates at point 1 as shown in the figure. However, during a severe contingency producing a voltage drop on the AC network 1 feeding the rectifier, the operating point moves to point 2. The rectifier therefore is forced to a minimum mode and the inverter will be in current control mode.

VDCOL Function

Another important control function is implemented to change the reference current according to the value of the DC voltage. This control, named Voltage Dependent Current Order Limiter (VDCOL), automatically reduces the reference current (Id_ref) set point when VdL decreases (as, for example, during a DC line fault or a severe AC fault). Reducing the Id reference currents also reduces the reactive power demand on the AC network, helping to recover from fault. The VDCOL parameters of the Discrete 12-Pulse HVDC Control block dialog box are explained by this diagram:

Figure 2-30: VDCOL Characteristic; Id_ref = f(VdL)

The Id_ref value starts to decrease when the Vd line voltage falls below a threshold value VdThresh (0.6 p.u.). The actual reference current used by the controllers is available at the fourth controller output, named Id_ref_lim. IdMinAbs is the absolute minimum Id_ref value, set at 0.08 p.u. When the DC line voltage falls below the VdThresh value, the VDCOL reduces instantaneously to Id_ref. However, when the DC voltage recovers, VDCOL limits the Id_ref rise time with a time constant defined by parameter Tup (80 ms in the example).

Current and Voltage Regulators

The rectifier and the inverter controls both have a voltage and a current regulator operating in parallel calculating firing angles v and i. The effective angle is the minimum value of v and i. This angle is available at the third block output, named alpha (deg). Both regulators are of the proportional- integral type. They should have high enough gains for low frequencies (<10 Hz) to maintain the current or voltage response equal to the reference current (Id_ref_lim) or reference voltage (Vd_ref), as long as is within the minimum and maximum limits (5º < < 165º for rectifier, 92º < < 165º for inverter). The regulator gains Kp and KI are adjusted during small perturbations in the current reference. The following gains are used:

Another particularity of the regulator is the linearization of the proportional gain. As the Vd voltage generated by the rectifier and the inverter is proportional to cos(), the Vd variation due to a change is proportional to sin(). With a constant Kp value, the effective gain is therefore proportional to sin(). In order to keep a constant proportional gain, independent of the value, the gain is linearized by multiplying the Kp constant with 1/sin(). This linearization is applied for a range of defined by two limits specified in the dialog box (third line).


  Frequency Response of the AC and DC Systems System Startup and Steady State