Instrument Control Toolbox    

Status and Event Reporting

GPIB provides a system for reporting status and event information. With this system, you can find out if your instrument has data to return, whether a command error occurred, and so on. For many instruments, the reporting system consists of four 8-bit registers and two queues (output and event). The four registers are grouped into these two functional categories:

The status registers, enable registers, and output queue are shown below.

The Status Byte Register

Each bit in the Status Byte Register (SBR) is associated with a specific type of event. When an event occurs, the instrument sets the appropriate bit to 1. You can enable or disable the SBR bits with the Service Request Enable Register (SRER). You can determine which events occurred by reading the enabled SBR bits. The SBR bits are described below.

Table 3-4: Status Byte Register Bits
Bit
 Label
 Description
0-3
 -
 Instrument-specific summary messages.
4
 MAV
 The Message Available bit indicates if data is available in the Output Queue. MAV is 1 if the Output Queue contains data. MAV is 0 if the Output Queue is empty.
5
 ESB
 The Event Status bit indicates if one or more enabled events have occurred. ESB is 1 if an enabled event occurs. ESB is 0 if no enabled events occur. You enable events with the Standard Event Status Enable Register.
6
MSS
 The Master Summary Status summarizes the ESB and MAV bits. MSS is 1 if either MAV or ESB is 1. MSS is 0 if both MAV and ESB are 0. This bit is obtained from the *STB? command.
RQS
 The Request Service bit indicates that the instrument requests service from the GPIB controller. This bit is obtained from a serial poll.
7
 -
 Instrument-specific summary message.

For example, if you want to know when a specific type of instrument error occurs, you would enable bit 5 of the SRER. Additionally, you would enable the appropriate bit of the Standard Event Status Enable Register (see the following section) so that the error event of interest is reported by the ESB bit of the SBR.

The Standard Event Status Register

Each bit in the Standard Event Status Register (SESR) is associated with a specific state of the instrument. When the state changes, the instrument sets the appropriate bits to 1. You can enable or disable the SESR bits with the Standard Event Status Enable Register (ESER). You can determine the state of the instrument by reading the enabled SESR bits. The SESR bits are described below.

Table 3-5: Standard Event Status Register Bits
Bit
 Label
 Description
0
 OPC
 The Operation Complete bit indicates that all commands have completed.
1
 RQC
 The Request Control bit is not used by most instruments.
2
 QYE
 The Query Error bit indicates that the instrument attempted to read an empty output buffer, or that data in the output buffer was lost.
3
 DDE
 The Device Dependent Error bit indicates that a device error occurred (such as a self-test error).
4
 EXE
 The Execution Error bit indicates that an error occurred when the device was executing a command or query.
5
 CME
 The Command Error bit indicates that a command syntax error occurred.
6
 URQ
 The User Request bit is not used by most instruments.
7
 PON
 The Power On bit indicates that the device is powered on.

For example, if you want to know when an execution error occurs, you would enable bit 4 of the ESER. Additionally, you would enable bit 5 of the SRER (see the preceding section) so that the error event of interest is reported by the ESB bit of the SBR.

Reading and Writing Register Information

This section describes the common GPIB commands used to read and write status and event register information.

Table 3-6: GPIB Commands for Reading and Writing Register Information
Register
 Operation
 Command
 Description
SESR
Read
 *ESR?
 Return a decimal value that corresponds to the weighted sum of all the bits set in the SESR register.
Write
 N/A
 You cannot write to the SESR register.
ESER
Read
 *ESE?
 Return a decimal value that corresponds to the weighted sum of all the bits enabled by the *ESE command.
Write
 *ESE
 Write a decimal value that corresponds to the weighted sum of all the bits you want to enable in the SESR register.
SBR
Read
 *STB?
 Return a decimal value that corresponds to the weighted sum of all the bits set in the SBR register. This command returns the same result as a serial poll except that the MSS bit is not cleared.
Write
 N/A
 You cannot write to the SBR register.
SRER
Read
 *SRE?
 Return a decimal value that corresponds to the weighted sum of all the bits enabled by the *SRE command.
Write
 *SRE
 Write a decimal value that corresponds to the weighted sum of all the bits you want to enable in the SBR register.

For example, to enable bit 4 of the SESR, you write the command *ESE 16. To enable bit 4 and bit 5 of the SESR, you write the command *ESE 48. To enable bit 5 of the SBR, you write the command *SRE 32.

To see how to use many of these commands in the context of an instrument control session, refer to Example: Executing a Serial Poll.


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