Communications Blockset    
Charge Pump PLL

Implement a charge pump phase-locked loop using a digital phase detector

Library

Synchronization

Description

The Charge Pump PLL (phase-locked loop) block automatically adjusts the phase of a locally generated signal to match the phase of an input signal. It is suitable for use with digital signals.

This PLL has these three components:

The input signal represents the received signal. The input must be a sample-based scalar signal. The three output ports produce:

A sequential logic phase detector operates on the zero crossings of the signal waveform. The equilibrium point of the phase difference between the input signal and the VCO signal equals . The sequential logic detector can compensate for any frequency difference that might exist between a VCO and an incoming signal frequency. Hence, the sequential logic phase detector acts as a frequency detector.

Dialog Box

Lowpass filter numerator
The numerator of the lowpass filter's transfer function, represented as a vector that lists the coefficients in order of descending powers of s.
Lowpass filter denominator
The denominator of the lowpass filter's transfer function, represented as a vector that lists the coefficients in order of descending powers of s.
VCO input sensitivity (Hz/V)
This value scales the input to the VCO and, consequently, the shift from the VCO quiescent frequency value. The units of VCO input sensitivity are Hertz per volt.
VCO quiescent frequency (Hz)
The frequency of the VCO signal when the voltage applied to it is zero. This should match the frequency of the input signal.
VCO initial phase (rad)
The initial phase of the VCO signal.
VCO output amplitude
The amplitude of the VCO signal.

See Also

Phase-Locked Loop

References

For more information about digital phase-locked loops, see the works listed in Selected Bibliography for Synchronization in Using the Communications Blockset.


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