DSP Blockset

Zero Algorithmic Delay

The FFT block is an example of a component that has no algorithmic delay; the Simulink timer does not record any passage of time while the block computes the FFT of the input, and the transformed data is available at the output in the same time step that the input is received. There are many other blocks that have zero algorithmic delay, such as the blocks in the Matrices and Linear Algebra libraries. Each of those blocks processes its input and generates its output in a single time step.

In Chapter 5, "DSP Block Reference," blocks are assumed to have zero delay unless otherwise indicated. In cases where a block has zero delay for one combination of parameter settings but nonzero delay for another, this is noted on the block's reference page.

Example: Zero Algorithmic Delay.   Create the model below to observe the operation of the zero-delay Normalization block.

Use the default settings for the Normalization, Digital Clock, Mux, and To Workspace blocks, and adjust the Signal From Workspace block parameters as follows:

• Signal = 1:100
• Sample time = 1/4
• Samples per frame = 4

Select Sample-based from the Output signal menu in the Frame Status Conversion block.

Note that the current value of the Simulink timer (from the Digital Clock block) is prepended to each output frame. The frame-based signal is converted to a sample-based signal by the Frame Status Conversion so that the output in the command window will be more easily readable.

In the example, the Signal From Workspace block generates a new frame containing four samples once every second (T_fo = *4). The first few output frames are shown below.

• (t=0)   [ 1  2  3  4]'
  (t=1)   [ 5  6  7  8]'
  (t=2)   [ 9 10 11 12]'
  (t=3)   [13 14 15 16]'
  (t=4)   [17 18 19 20]'
  

When you run the simulation, the normalized output, yout, is saved in a workspace array. To convert the array to an easier-to-read matrix format, type

• squeeze(yout)'
  

The first few samples of the result, ans, are shown below:

The first column of ans is the Simulink time provided by the Digital Clock block. You can see that the squared 2-norm of the first input,

• [1 2 3 4]' ./ sum([1 2 3 4]'.^2)
  

appears in the first row of the output (at time t=0), the same time step that the input was received by the block. This indicates that the Normalization block has zero algorithmic delay.

Algorithmic Delay

Zero Algorithmic Delay and Algebraic Loops