DSP Blockset

Algorithmic Delay

Algorithmic delay is delay that is intrinsic to the algorithm of a block or subsystem, and is independent of CPU speed. In Chapter 5, "DSP Block Reference," and elsewhere in this guide, the algorithmic delay of a block is referred to simply as the block's delay. It is generally expressed in terms of the number of samples by which a block's output lags behind the corresponding input. This delay is directly related to the time elapsed on the Simulink timer during that block's execution.

The algorithmic delay of a particular block may depend on both the block's parameter settings and the general Simulink settings. To simplify matters, it is helpful to categorize a block's delay using the following levels:

• Zero algorithmic delay
• Basic algorithmic delay
• Excess algorithmic delay (tasking latency)

The following sections explain the different levels of delay, and how the simulation and parameter settings can affect the level of delay that a particular block experiences.

Reducing Computational Delay

Zero Algorithmic Delay