Communications Blockset

Blocks and Subsystems in the Model

Most of the blocks in this model function in the same way as they do in the PLL-Based Frequency Synthesis Demo. You can refer to the documentation for that model for more information about these blocks function. There are two subsystems in this example that are not present in the Phase-Locked Frequency Synthesis demo. They are labeled "Accumulator" and "Divide Frequency."

Accumulator

The Accumulator subsystem repeatedly adds the constant m to a cumulative sum. While the sum is less than 1, the output labelled "Carry" is 0. At a time step when the sum becomes greater than or equal to 1, the carry output is 1 and the cumulative sum is reset to its fractional part. The fraction of the time when the carry output is 1 is equal to m, while the fraction of the time when it is 0 is equal to 1-m.

Divide Frequency

The Divide Frequency subsystem divides the frequency of the synthesized signal by n when the output of the Accumulator subsystem is 0, and divides it by n+1 when the output is 1. As a result, the average amount that frequency is divided by is

(1-m)n + m(n+1) = n + m = 10.3

The line leading out of the Divide Frequency subsystem is labeled "Divided synthesized." At steady state, when the frequency of the synthesized signal is 103 MHz, the divided synthesized signal has an average frequency of 10 Mhz.

Variables in the Model

Phase Detector