CDMA Reference Blockset    
IS-95A Fwd Ch Scrambler

Scramble the data on the Paging and forward Traffic channels by the decimated long code and insert power control bits into the Traffic channel

Library

IS-95A Base Station Transmitter

Description


This block scrambles and inserts power control bits into the input data stream. The scrambling function is applicable to Paging and forward Traffic channels. The power bit insertion, which applies only to the Traffic channel, occurs at an 800 Hz data rate. For the case of the Sync channel, this block does not scramble or insert power bits; instead, it merely repeats the input symbol four times to operate the Sync channel output at 19.2 ksps.

To scramble the Frame In data, this block first combines it with the decimated Long Code input data modulo two, and then replaces some bits with the Power Bits input data. The Traffic channel Rate Set I and Rate Set II include two and one power control bits, respectively, per power group (a group of 24 symbols). In case of Rate Set I, the power bits are inserted in two consecutive symbol locations. The last four decimated long code bits in a power group determine the power bit insertion position in the next power group.

Finally, this block adjusts the power level for the Paging and Traffic channel data bits, to take into account the power levels for rates lower than full rate, before they are output.

This block operates at the sample time of the Data In signal. The Power Bits input signal has a slower sample time.

Inputs

Rate
Integer scalar that specifies the data rate for the input signal. To indicate a rate fraction of Full, Half, Quarter, or Eighth, use an input value of 0, 1, 2, or 3, respectively. The table below shows all valid channel types and rate fractions, along with their associated data rates and Rate input values.

Channel Type
 Data Rate (bps)
 Input Value
Sync (always Eighth rate)
 1200
 3
Paging, Full
 9600
 0
Paging, Half
 4800
 1
Access (always Half rate)
 4800
 1
Traffic, Rate Set I, Full
 9600
 0
Traffic, Rate Set I, Half
 4800
 1
Traffic, Rate Set I, Quarter
 2400
 2
Traffic, Rate Set I, Eighth
 1200
3
Traffic, Rate Set II, Full
 14400
 0
Traffic, Rate Set II, Half
 7200
 1
Traffic, Rate Set II, Quarter
 3600
 2
Traffic, Rate Set II, Eighth
 1800
 3
Data In
Binary scalar representing the frame symbol to be scrambled.
Long Code
Real scalar of bipolar data representing the decimated long code bit used for scrambling of the input data and determining the power bit location.
Power Bits
Binary scalar representing the power control bit.

Outputs

Real vector or scalar of bipolar data that represents the scrambled data and inserted power bit symbols or repeated symbols. The default size is four for the Sync channel and one for the Paging and Traffic channels.

Dialog Box

Parameters

Rate set
The rate set, either Rate Set I or Rate Set II.
Channel type
The channel type, either Sync, Paging, or Traffic.

See Also

IS-95A Fwd Ch Descrambler
IS-95A Long Code Generator
IS-95A Forward Traffic Channel Detection Demo

Specification References

IS-95A 7.1.3.1.6
J-STD-008 3.1.3.1.7


 IS-95A Fwd Ch Repeater/Derepeater IS-95A Fwd Ch Viterbi Decoder