Embedded Target for Texas Instruments C6000 DSPs | ![]() ![]() |
Compute the decimation-in-frequency forward FFT of a complex input vector
Library
Description
The FFT block computes the decimation-in-frequency forward FFT, with interstage scaling, of each channel of a complex input signal. The input length of each channel must be both a power of two and in the range 8 to 16,384, inclusive. The input must also be in natural (linear) order. The output of this block is a complex signal in natural order. Inputs and outputs are all signed 16-bit fixed-point data types.
The fft16x16r
routine used by this block employs butterfly stages to perform the FFT. The number of butterfly stages used, S, depends on the input length L = 2^k. If k is even, then S = k/2. If k is odd, then S = (k+1)/2.
If k is even, then L is a power of two as well as a power of four, and this block performs all S stages with radix-4 butterflies to compute the output. If k is odd, then L is a power of two but not a power of four. In that case this block performs the first (S-1) stages with radix-4 butterflies, followed by a final stage using radix-2 butterflies.
To minimize noise, the FFT block also implements a divide-by-two scaling on the output of each stage except for the last. Therefore, in order to ensure that the gain of the block matches that of the theoretical FFT, the FFT block offsets the location of the binary point of the output data type by (S-1) bits to the right relative to the location of the binary point of the input data type. That is, the number of fractional bits of the output data type equals the number of fractional bits of the input data type minus (S-1).
The FFT block supports both continuous and discrete sample times. This block supports little-endian code generation.
Dialog Box
Algorithm
In simulation, the FFT block is equivalent to the TMS320C62x DSP Library assembly code function DSP_fft16x16r
. During code generation, this block calls the DSP_fft16x16r
routine to produce optimized code.
See Also
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