IS-95A CRC Generator (CDMA Reference Blockset)

Generate Cyclic Redundancy Check (CRC) bits and append them along with tail bits to an input data frame

Library

IS-95A Common

Description

This block generates the Cyclic Redundancy Check (CRC) bits in accordance with the IS-95A standard. The block then appends the CRC bits and tail bits to the input information bits to generate the output frame. The generator polynomial used to generate the CRC bits is specified in the IS-95A standard.

The number of relevant information bits may vary from frame to frame, depending on the type of channel and the data rate; therefore, the size of the Frame In port has been set to the maximum size of 268 (Rate Set II, Traffic Full Rate). Also, the number of bits added depends on the channel, rate set, and rate. Hence, the output port size has been set to the maximum value of 288 (Rate Set II, Traffic Full Rate). The numbers for the relevant input and output bits are specified in the table below.

The CRC and tail bits immediately follow the relevant information bits. The tail bits are used in the decoding of the convolutionally coded data at the receiver. These are all zeros and are added only in the case of the Traffic and Access channels. The bits of the 288 that are output and that do not correspond to the relevant bits for the data rate in use, are cleared to zero.

Channel Type
Number of Relevant Input Bits
Number of CRC Bits
Number of Tail Bits
Number of Relevant Output Bits

Sync, Eighth Rate
32
0
0
32

Paging, Full Rate
192
0
0
192

Paging, Half Rate
96
0
0
96

Access
88
0
8
96

Traffic, Rate Set I, Full Rate
172
12
8
192

Traffic, Rate Set I, Half Rate
80
8
8
96

Traffic, Rate Set I, Quarter Rate
40
0
8
48

Traffic, Rate Set I, Eighth Rate
16
0
8
24

Traffic, Rate Set II, Full Rate
268
12
8
288

Traffic, Rate Set II, Half Rate
126
10
8
144

Traffic, Rate Set II, Quarter Rate
56
8
8
72

Traffic, Rate Set II, Eighth Rate
22
6
8
36

Channel Type	Number of Relevant Input Bits	Number of CRC Bits	Number of Tail Bits	Number of Relevant Output Bits
Sync, Eighth Rate	32	0	0	32
Paging, Full Rate	192	0	0	192
Paging, Half Rate	96	0	0	96
Access	88	0	8	96
Traffic, Rate Set I, Full Rate	172	12	8	192
Traffic, Rate Set I, Half Rate	80	8	8	96
Traffic, Rate Set I, Quarter Rate	40	0	8	48
Traffic, Rate Set I, Eighth Rate	16	0	8	24
Traffic, Rate Set II, Full Rate	268	12	8	288
Traffic, Rate Set II, Half Rate	126	10	8	144
Traffic, Rate Set II, Quarter Rate	56	8	8	72
Traffic, Rate Set II, Eighth Rate	22	6	8	36

Inputs

Rate

Integer scalar that specifies the data rate for the input signal. To indicate a rate fraction of Full, Half, Quarter, or Eighth, use an input value of 0, 1, 2, or 3, respectively. The table below shows all valid channel types and rate fractions, along with their associated data rates and Rate input values.


Channel Type	Data Rate (bps)	Input Value
Sync (always Eighth rate)	1200	3
Paging, Full	9600	0
Paging, Half	4800	1
Access (always Half rate)	4800	1
Traffic, Rate Set I, Full	9600	0
Traffic, Rate Set I, Half	4800	1
Traffic, Rate Set I, Quarter	2400	2
Traffic, Rate Set I, Eighth	1200	3
Traffic, Rate Set II, Full	14400	0
Traffic, Rate Set II, Half	7200	1
Traffic, Rate Set II, Quarter	3600	2
Traffic, Rate Set II, Eighth	1800	3

Frame In

Binary vector of size 268 that contains the input frame to which the block appends the CRC and tail bits.

Outputs

Binary vector of size 288. The relevant bits of the output include the input bits, the CRC bits, and the tail bits, in that order.

Dialog Box

Parameters

Rate set: The rate set, either Rate Set I or Rate Set II.
Channel type: The forward or reverse channel type, either Sync, Paging, Access, or Traffic.

Specification References

IS-95A 6.1.3.3.2, 7.1.3.5.2
J-STD-008 2.1.3.3.2.1, 3.1.3.5.2.1

Alphabetical List of Blocks IS-95A Frame Quality Detector